CSA Technical Reports Archive

[ Year Index | List All TRs ]

(Example: 2005-1 or 2005 1 or 2005)

Recent Technical Reports

Thread-Local Semantics for Datarace-free Programs and its Sequential Abstractions
Suvam Mukherjee, Oded Padon, Sharon Shoham, Deepak D'Souza, Noam Rinetzky, Mooly Sagiv
Refining Cache Behavior Prediction Using Cache Miss Paths
Kartik Nagar, Y.N.Srikant
Detecting All High-Level Dataraces in an RTOS Kernel
Suvam Mukherjee, Arun Kumar and Deepak D'Souza
DPAssist: Automated Feedback Generation for Iterative Dynamic Programming Assignments
Shalini Kaleeswaran, Anirudh Santhiar, Aditya Kanade, Sumit Gulwani

2015-6 Temporarily Removed

Falcon: A Graph Manipulation Language for Heterogeneous Systems
Unnikrishnan C, Y.N.Srikant & Rupesh Nasre
A theory of refinement for ADT's with functional interfaces
Sumesh Divakaran, Deepak D'Souza, Prahladavaradan Sampath, Nigamanth Sridhar, and Jim Woodcock
Polymage: Automatic Optimization for Image Processing Pipelines
Ravi Teja Mallapudi, Vinay Vasista & Uday Bondhugula
Efficient Compilation of Stream Programs for Heterogeneous Architectures: A Model-Checking based approach
Rajesh Kumar Thakur & Y.N.Srikant
Shared Instruction Cache Analysis in Real-time Multi-core Systems
Kartik Nagar & Y.N.Srikant
Automatic Intra-Array Storage Optimization
Somashekaracharya G Bhaskaracharya, Uday Bondhugula & Albert Cohen
Effective Automatic Data Allocation for Parallelization of Affine Loop Nests
Chandan Reddy and Uday Bondhugula
Handling Negative Coefficients in Automatic Transformation Schedules
Uday Bondhugula and Albert Cohen
A Compositional Refinement Technique for Verifying Abstract Data Type Implementations
Sampath, Nigamanth Sridhar, and Jim Woodcock
Extraction of Robust Voids and Pockets in Proteins
Raghavendra Sridharamurthy, Harish Doraiswamy, Siddharth Patel, Raghavan Varadarajan, and Vijay Natarajan
Exploiting Critical Data Regions to Reduce Data Cache Energy Consumption
Ananda Vardhan , Y.N.Srikant
A clock-optimal hierarchical monitoring automaton construction for MITL
Raj Mohan & Deepak D'Souza
Modeling Statement Context to Surface even Rare Diffused Topics Automatically
Suparna Bhattacharya, Mrinal Kanti Das, Chiranjib Bhattacharyya, K. Gopinath
Interdependent Cache Analyses for better precision and Safety
Kartik Nagar & Y N Srikant
Model-checking bisimulation-based information flow properties for pushdown systems
Deepak D'souza & K.R.Raghavendra
TCP: Thread Contention Predictor for Parallel Programs
Aparna Mandke, Bharadwaj Amrutur, Y. N. Srikant and Chiranjib Bhattacharyya
Scalable Working Set Estimation Method for Chip Multicores Using Tagged Bloom Filter And Its Applicaions
Aparna Mandke, Bharadwaj Amrutur & Y N Srikant
Adaptive Power Optimization of Onchip SNUCA Cacheon Tiled Chip Multicore Architecture using Remap Policy
Aparna Mandke, Bharadwaj Amrutur & Y N Srikant
A Framework for Online Visualization and Simulation of Critical Weather Applications
Preeti Malakar, Vijay Natarajan & Sathish S Vadhiyar
Dataflow Analysis for Datarace-free Programs
Arnab De, Deepak D'Souza & Rupesh Nasre
Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures
Aparna Mandke, Bharadwaj Amrutur & Y.N.Srikant
Conflict-Tolerant Specifications for Hybrid Systems
Deepak D' Souza, Madhu Gopinathan, S.Ramesh, Prahladavaradan Sampath
Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes
R.C.Hansdah, Deepak Ravi, Sahebrao Sidram Baiger, Amulya Ratna
Sapphire: A Framework to Explore Power/Performance Implications of Tiled Architecture on Chip Multicore Platform
Aparna Mandke, Keshavan Varadarajan, Basavaraj Talwar, Bharadwaj Amruthur and Y.N.Srikant
Petrinet based Performance Modeling for Effective DVFS for Multithreaded Programs
Arun R and Y.N.Srikant
Pragmatic Data Mining: Novel Paradigms for Tackling Key Challenges
Vikas Garg, M.Narasimha Murthy
Accelerating Multi-core Simulators
Aparna Mandke, Keshavan Varadarajan, Amrutur Bhardwaj, Y.N.Srikant

Conflict-Tolerant Real-Time Specifications in Metric Temporal Logic
Sumesh Divakaran, Deepak D'Souza, Raj Mohan M.
Conflict-Tolerant Specifications in Temporal Logic
Sumesh Divakaran, Deepak D'Souza, Raj Mohan M.
Popular Matchings with variable job capacities
Telikepalli Kavitha and Meghana Nasre
A Computational Procedure for General-sum Stochastic Games
Prasad H. L., S. Bhatnagar, N. Hemachandra


Analysing Message Sequence Graph Specifications
Joy Chakraborty, Deepak D'Souza, K. Narayan Kumar
Counter-free input-determined timed automata
Fabrice Chevalier, Deepak D'Souza, Pavithra Prabhakar

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Hard Copies

Requests for hard copies of technical reports must be addressed to the CSA office.
E-mail address: office@csa.iisc.ernet.in
Postal address: Computer Science and Automation
Indian Institute of Science
Bangalore - 560 012
Karnataka, India.

Please indicate the TR number, the title and the authors.

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[Updated at 2009-10-22T06:42Z]