http://www.csa.iisc.ernet.in/ Computer Science and Automation: News, Events, Seminars. http://www.csa.iisc.ernet.in/sem-evts/seminars.php#2012-05-30-1130-03


Department of Computer Science and Automation

Ph.D. Thesis Defense







Speaker : Mr. Rogers Mathew



Title : Boxicity and Cubicity: A Study on Special

Classes of Graphs



Faculty Advisor : Prof. Sunil Chandran



Date : Wednesday, May 30, 2012



Time : 11:30 AM



Venue : CSA Seminar Hall (Room No. 254, First Floor)



Live Video : MMCRs - ECE, CEDT, EE

or

URL -- http://mmcr.iisc.ernet.in:8008/live/csa.html



Abstract



Let F be a family of sets. A graph G(V,E) is an intersection graph of

sets from F if there exists a function f:V(G) -> F such that (u,v) in

E(G) <=> f(u) and f(v) have a nonempty intersection. An "interval

graph" is an intersection graph of a family of closed intervals on the

real line. Interval graphs find application in diverse fields ranging

from DNA analysis to VLSI design.





An interval on the real line can be generalized to a "k dimensional

box" or "k-box''. A k-box B=(R_1,R_2,...,R_k) is defined to be the

Cartesian product R_1 x R_2 x ... x R_k, where each R_i is a closed

interval on the real line. If each R_i is a unit length interval, we

call B a "k-cube''. A graph G has a "k-box representation", if G is an

intersection graph of a family of k-boxes in R^k. The minimum k such

that G has a k-box representation is the "boxicity" of G (box(G)).

Similarly, the "cubicity" of G (cub(G)) is the minimum integer k such

that G has a k-cube representation.



The concepts of boxicity and cubicity were introduced by F.S. Roberts

in 1969. Deciding whether the boxicity (or cubicity) of a graph is at

most k is NP-complete even for a small positive integer k. Box

representation of graphs finds application in niche overlap

(competition) in ecology and to problems of fleet maintenance in

operations research. Given a low dimensional box representation, some

well known NP-hard problems become polynomial time solvable.



In this thesis, we present several upper bounds for boxicity and

cubicity of special classes of graphs in terms of other graph

parameters.



Our Work:



1. We show that, for a k-degenerate graph G, cub(G) is O(k log(n)).

This bound is tight. We also give an efficient deterministic algorithm

to construct an O(k log(n)) dimensional cube representation.



2. Crossing number of a graph G is the minimum number of crossing

pairs of edges, over all drawings of G in the plane. We find a

non-trivial relation between the boxicity of a graph and its crossing

number.



3. Almost all graphs have cubicity O(d log n), where 'd' denotes the

average degree.



4. Boxicity of a line graph with maximum degree D is O(D log(log(D))).

We also prove a non-trivial lower bound for the boxicity of a

d-dimensional hypercube.



5. Boxicity of a k-leaf power is at most k-1. For every k, there exist

k-leaf powers whose boxicity is exactly k − 1. Since leaf powers are a

subclass of strongly chordal graphs, this result implies that there

exist strongly chordal graphs with arbitrarily high boxicity.



6. We give a constructive proof to show that there exist chordal

bipartite graphs with arbitrarily high boxicity.









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Department of Computer Science and Automation

M.Sc. (Engg) Colloquium







Speaker : Mr. Pankaj Pipada



Title : Studies in Autonomic Management of Storage Systems



Faculty Advisor : Prof. K. Gopinath



Date : Thursday, May 17, 2012



Time : 3:00 PM



Venue : CSA Seminar Hall (Room No. 254, First Floor)



Live Video : MMCRs - ECE, CEDT, EE

or

URL -- http://mmcr.iisc.ernet.in:8008/live/csa.html



Abstract



Autonomic management is important in storage systems and the space of autonomics in storage systems is vast. Such autonomic management systems can employ a variety of techniques depending upon the specific problem. In this thesis, we first take an algorithmic approach towards reliability enhancement and then we use learning along with a reactive framework to facilitate storage optimization for applications.



We study how the reliability of non-repairable systems can be improved through automatic reconfiguration of their XOR-coded structure. To this regard we propose to increase the fault tolerance of non-repairable systems by reorganizing the system, after a failure is detected, to a new XOR-code with a better fault tolerance. As errors can manifest during reorganization due to whole reads of multiple submodules, our framework takes them into account and models such errors as based on access intensity (ie. BER - bit error rate). We present and evaluate the reliability of an example storage system with and without reorganization.



Motivated by the critical need for automating various aspects of data management in virtualized data centers, we study the specific problem of automatically implementing Virtual Machine (VM) migration in a dynamic environment according to some pre-set policies. This is a problem that requires automated identification of various workloads and their execution environments running inside virtual machines in a non-intrusive manner. To this end we propose AuM (for Autonomous Manager)that has the capability to learn workloads by aggregating variety of information obtained from network traces of storage protocols. We use state of the art Machine Learning tools, namely Multiple Kernel learning, to aggregate information and show that AuM is indeed very accurate in identifying workloads, their execution environments and is also successful in following user set policies very closely for the VM migration tasks.



Storage infrastructure in large-scale cloud data center environments must support applications with diverse, time-varying data access patterns while observing the quality of service. To meet service level requirements in such heterogeneous application phases, storage management needs to be phase-aware and adaptive, i.e., identify specific storage access patterns of applications as they occur and customize their handling accordingly. We build LoadIQ, an online application phase detector for networked (file and block)storage systems. In a live deployment, LoadIQ analyzes traces and emits phase labels learnt online. Such labels could be used to generate alerts or to trigger phase-specific system tuning.









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Department of Computer Science and Automation

Department Seminar







Speaker : Mr Ravi Trivedi (CSA Alumnus)

Principal Officer

Southeast Interactive Technology Funds



Title : Entrepreneurship as a Career Option



Date : Friday, May 11, 2012



Time : 3:30 PM



Venue : CSA Seminar Hall (Room No. 254, First Floor)



Live Video : MMCRs - ECE, CEDT, EE

or

URL -- http://mmcr.iisc.ernet.in:8008/live/csa.html



Abstract



The talk will focus on choosing Entrepreneurship as a career

option, and delves into the nuances before and after one makes the

choice. The talk will highlight best practices, and present a framework

to think about how to reach this decision, and what to do when want to

do your startup.



Outline of topics that will be discussed in the talk:

a) Why, When, Who, Thoughts and Pros/Cons on entrepreneurship

b) Making the Leap

c) Types of startups

d) First Steps: Founding Team, Idea, Building Product,

Selling your Product

e) Fund raising

f) Work life balance as a founder



Biography of the speaker



Ravi works as a Principal at Southeast Interactive Technology Funds, an

early stage technology venture capital fund. He runs Srijan Capital, a seed

stage fund to make angel investments and incubate startups in India. He is a

charter member of TiE Bangalore, and likes to work in trenches with

passionate entrepreneurs. At Southeast, apart from investments, his

experience includes running and growing a B2C E-commerce startup.



Before Southeast, Ravi worked as equity analyst with Banc of America

Securities, where he participated in covering companies over $120B in market

capitalization. He was part of the team that was ranked runners up in the

Alpha Hedge Fund Research rankings.



Ravi started his career as a software engineer at Hewlett Packard and has

global cross-functional experience in leading and managing technology

businesses. He has worked in marketing, consulting and engineering

functions at Hewlett Packard. Ravi co-authored the book Web Services

Security, and was HP's representative in few web services standards.



Ravi completed his MBA from Duke University, Fuqua School of Business and

has a Masters in Computer Science from Computer Science and

Automation, Indian Institute of Science, Bangalore.



Host Faculty : Prof. Y. Narahari









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Department of Computer Science and Automation

Ph.D. Colloquium







Speaker : Aparna Mandke



Title : Power Efficient Last Level Cache for Chip-Multicores



Faculty Advisor : Y.N. Srikant and Bharadwaj Amrutur



Date : Tuesday, May 15, 2012



Time : 4:00 PM



Venue : CSA Seminar Hall (Room No. 254, First Floor)



Live Video : MMCRs - ECE, CEDT, EE

or

URL -- http://mmcr.iisc.ernet.in:8008/live/csa.html



Abstract



The number of cores and on-chip cache size have been increasing in chip multicores

(CMPs), thanks to advances in technology. As a result, leakage power dissipated in

the on-chip cache has become a major contributing component of the power dissipated

in the memory subsystem. In this thesis, we explore various techniques to switch-off

the over-allocated cache so as to reduce leakage power consumed by it.



Past studies for leakage power reduction techniques have focused on smaller

uniform access latency primary caches, with a single application executing on

a uniprocessor. In this thesis, we consider large caches inter-connected using

an on-chip network on CMPs. Such a cache offers non-uniform access latency to

different cores present on the CMP. Hence, it is called as a Non-Uniform Cache

Architecture (NUCA). The concurrently executing multiple threads and NUCA

cache make leakage power optimization on CMPs a challenging problem. We first

propose a new method to estimate the working set size of an application(s)

executing on a CMP. We use this method to adapt associativity of NUCA caches on

tiled CMPs. Our algorithm uses information available locally in each tile. This

enables the technique to scale with the number of cores present on a CMP.



We also propose the remap strategy in which farther L2 slices are mapped

to nearer L2 slices. The mapped L2 slices are switched-off. Apart from

reducing leakage power consumption in L2 slices, it also saves execution time

in some applications. Next, we determine the maximum energy-delay savings

possible with the remap strategy using genetic algorithms. We formulate the near-optimal

remap configuration determination problem as a energy-delay minimization

problem.



Leakage power optimization policies can be applied to static or

dynamic NUCA policies. However, the characteristics of an application decide

the suitability of the cache access policy. Hence, we propose indices to

quantify data sharing properties of an application. We use these indices to

predict suitability of a cache access policy for an application.



Biography of the speaker



Aparna Mandke is a PhD student in the department of Computer Science and

Automation.



Host Faculty : Y.N. Srikant









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Department of Computer Science and Automation

Department Seminar







Speaker : Dr. Sagar Chaki



Title : Verifying Periodic Real-Time Software



Date : Monday, June 11, 2012



Time : 4:00 PM



Venue : CSA Seminar Hall (Room No. 254, First Floor)



Live Video : MMCRs - ECE, CEDT, EE

or

URL -- http://mmcr.iisc.ernet.in:8008/live/csa.html



Abstract



Real-Time Embedded Systems (RTESs) constitute an important sub-class of concurrent safety-critical software. In this

talk, I will consider the problem of verifying functional correctness of periodic RTES, a popular variant of RTES that

execute periodic tasks in an order determined by Rate Monotonic Scheduling (RMS). A computational model of a periodic

RTES is a finite collection of terminating tasks that arrive periodically and must complete before their next arrival. I

will present an approach -- developed in joint work with Arie Gurfinkel and Ofer Strichman -- for time-bounded

verification of safety properties in periodic RTES. Our approach is based on sequentialization. Given an RTES C and a

time-bound B, we construct (and verify) a sequential program S that over-approximates all executions of C up to time B,

while respecting priorities and bounds on the number of preemptions implied by RMS. Our algorithm supports partial-order

reduction, preemption locks, and priority locks. We implemented our approach for C programs, with properties specified

via user-provided assertions. We evaluated our tool on several realistic examples, and were able to detect a subtle

concurrency issue in a robot controller. I will conclude with a summary of ongoing work and future directions.



Biography of the speaker



Sagar Chaki is a senior Member of Technical Staff at the Software Engineering

Institute at Carnegie Mellon University. He received a B.Tech in Computer

Science & Engineering from the Indian Institute of Technology, Kharagpur in

1999, and a Ph.D. in Computer Science from Carnegie Mellon University in 2005.

He works mainly on automating formal techniques for software analysis, but is

generally interested in rigorous and automated approaches for improving software

quality. He has developed several automated software verification tools,

including two model checkers for C programs, MAGIC and Copper. He has

co-authored over 40 peer reviewed publications. More details about Sagar and his

current work are available at http://www.sei.cmu.edu/staff/chaki. An up to date

list of his publications and a resume are available at

http://www.contrib.andrew.cmu.edu/~schaki and

http://www.contrib.andrew.cmu.edu/~schaki/resume.pdf.



Host Faculty : Aditya Kanade









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